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Course: Introduction to Zynq® devices with the Zynq-7000 family
The Zynq®-7000 family is a Xilinx® device family based on the Xilinx All Programmable SoC (System on Chip) architecture. It combines a Processing System (PS) formed around a dual-core ARM® Cortex™-A9 processor with a Programmable Logic (PL) which is equivalent to an FPGA.
Note: Xilinx has introduced in 2016 the Zynq-7000S with a single-core ARM cortex-A9 in the PS and an Artix-7 fabric in the PL.
Figure 1 - Simplified model of the Zynq architecture
“The processors in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration” . This means that you can configure (i.e. program) the PL form the PS. The PS can even operates without the PL turned on.
Zynq Programmable Logic (PL)
The Programmable Logic (PL) part of the Zynq has the same fabric as the 7series FPGAs. As shown in the Figure 2, some of the devices from the Zynq-7000 family have a PL equivalent to an Artix-7 Xilinx FPGA and the others have a PL equivalent to a Kintex-7 Xilinx FPGA.
Figure 2 - Zynq-7000 - Programmable Logic Features – (Source )
Zynq Processing System (PS)
The Zynq Processing System (PS) is a fixed piece of silicon and does not change in capability or size in all the devices of the Zynq-7000 family.
Figure 3 - 7ynq-7000 All Programmable SoC Simplified Overview
The Figure 3 shows a simplified overview of the Zynq-7000 family Processing System (PS). We can see that the PS comprises four major blocks:
- Application Processor Unit (APU) which includes the dual-core ARM® Cortex™-A9 processor
- Memory Interfaces
- I/O Peripherals (IOP)
Application Processor Unit (APU)
Figure 4 - APU overview (source: )
The key features of the APU include a Dual-core ARM Cortex-A9 MPCores, an Accelerator coherency port (ACP) interface, a Level 2 cache (512 KB), Dual-ported, on-chip RAM (OCM), an 8-channel DMA, Interrupts and Timers and a CoreSight debug and trace support for Cortex-A9.
The memory interface unit includes a dynamic memory controller and static memory interface modules. The dynamic memory controller supports DDR3, DDR3L, DDR2, and LPDDR2 memories. The static memory controllers support a NAND flash interface, a Quad-SPI flash interface, a parallel data bus, and a parallel NOR flash interface.
The APU, memory interface unit, and the IOP are all connected to each other and to the PL through a multi-layered ARM AMBA AXI interconnect. The interconnect is non-blocking and supports multiple simultaneous master-slave transactions.
The IOP unit contains the data communication peripherals (two Ethernet MAC peripherals, two USB 2.0 peripherals, two CAN bus interface controllers, two SD/SDIO controllers, two full-duplex SPI ports, two UARTs, two master and slave I2C interfaces and up to 118 GPIO bits(General Purpose IO)).
The IOP peripherals communicate to external devices using the dedicated multiuse I/O (MIO) pins (up to 54 pins depending on the device). All MIO pins support 1.8V HSTL and LVCMOS standards as well as 2.5V/3.3V standards.
Multiuse I/O (MIO)
Figure 5 - MIO Module Block Diagram (source: )
The function of the MIO is to map the PS peripheral ports to the PS pins of the device. This mapping can be defined using a GUI in the Vivado Design Suite. The MIO pins are split across two independently configured sets of I/O buffers: Bank 0, MIO[15:0] and Bank 1, MIO[53:16] (these pins are fixed, you cannot use any pins of the device).
Xilinx, “UG585 (v1.10) - Zynq-7000 AP SoC Technical Reference Manual,” 2015.
Xilinx, “DS190 - Zynq-7000 All Programmable SoC Overview (v1.9),” 2016.